A liquid crystal display has various merits such as compactness, thinness, low power consumption and lightness and is widely used in a variety of electronic equipment. In particular, an active matrix liquid crystal display including a thin film transistor (TFT) as a switching element of each pixel has display performance equivalent to that of a CRT, and therefore, it is widely used in OA equipment such as a personal computer, AV equipment such as a television and a cellular phone. Particularly, the performance has been recently rapidly improved for attaining a large screen size, high refinement and a high aperture ratio.
With respect to an active matrix liquid crystal display thus applied in more fields, there is a demand for a lower price. In particular, various examinations have been made on methods for lowering the price by reducing the fabrication cost through improvement of productivity of a TFT array substrate included in an active matrix liquid crystal display, and among these methods, a method for reducing the number of photolithography processes employing photolithography, that is one of fabrication processes for a TFT array substrate, has been widely studied.
The photolithography process includes a series of steps of (1) applying a resist on a substrate having a thin film thereon; (2) forming a latent image of a mask pattern on the resist through optical exposure using a photomask; (3) patterning the resist through development and etching the thin film; and (4) removing the resist. This is an indispensable fabrication process in the fabrication of a TFT array substrate.
For example, each of Patent Documents 1, 2, 3 and 4 discloses a method for fabricating a transmission TFT array substrate in which the number of photolithography processes is reduced to four.
Also, each of Patent Documents 5, 6, 7 and 8 discloses a method for fabricating a transmission TFT array substrate in which the number of photolithography processes is reduced to three.
However, each of Patent Documents 5, 6 and 8 makes no detailed description on formation of a pixel electrode included in a pixel or an external leading electrode, and when the formation of such an element is considered, at least one photolithography process is necessary, which makes the number of photolithography processes four or more.
Moreover, Patent Document 7 discloses a method for fabricating a top-gate type TFT array, in which a channel portion of a semiconductor layer included in a TFT is not masked from light entering through an insulating substrate. Therefore, this technique has a problem that a photodielectric leakage current is caused so as to disadvantageously lower an on/off ratio (that is, a ratio between a current passing in an on state and a leakage current caused in an off state in switching a drain current in accordance with a gate voltage).
Furthermore, as known technique employed in a conventional liquid crystal display, a masking region designated as a black matrix is formed by using chromium or a black resin on a counter substrate disposed to oppose a TFT array substrate so as to overlay TFTs, gate lines and source lines provided on the TFT array substrate, and the TFT array substrate and the counter substrate are aligned to each other so as to prevent light from entering the TFTs and suppress occurrence of a photodielectric leakage current.
However, in consideration of an alignment margin in aligning the TFT array substrate and the counter substrate, it is necessary to form a large masking region, which disadvantageously lowers the aperture ratio of a pixel.
Therefore, in an attempt made to suppress the lowering of the aperture ratio of a pixel, a black matrix of a counter substrate is omitted by forming a masking film like a black resist on a TFT array substrate so as to cover TFTs, gate lines and source lines, so that the TFT array substrate and the counter substrate can be easily aligned.
Thus, the number of photolithography processes necessary to perform in the fabrication of the TFT array substrate is further increased by one for forming the masking film.
As described so far, at least four or more photolithography processes are necessary to perform in the fabrication of a TFT array substrate included in a transmission liquid crystal display.
In a liquid crystal display with a comparatively large screen used in a monitor of a personal computer or a liquid crystal television, vertical alignment (VA) having a multi-domain, that is, what is called MVA (multi-domain vertical alignment), has been recently widely spread (see, for example, Patent Documents 9, 10 and 11).
In an MVA liquid crystal display, at least either a pixel electrode provided on a TFT array substrate or a common electrode provided on a counter substrate is provided with a cut pattern (an electrode opening) or a projection for controlling orientation of liquid crystal molecules. In the MVA liquid crystal display, a wide viewing angle is realized by dispersing orientation directions of liquid crystal molecules in a pixel by using a fringe field formed by the cut pattern or inclined orientation of the liquid crystal molecules obtained on an inclined portion of the projection.
Also with respect to such an MVA liquid crystal display with high display quality, it is desired to lower the fabrication cost for lowering the price by reducing the number of photolithography processes for improving the productivity of a TFT array substrate as described above.
Patent Document 1: Japanese Laid-Open Patent Publication No. 9-152626
Patent Document 2: Japanese Laid-Open Patent Publication No. 9-236827
Patent Document 3: Japanese Laid-Open Patent Publication No. 2000-258799
Patent Document 4: Japanese Laid-Open Patent Publication No. 2001-5038
Patent Document 5: Japanese Laid-Open Patent Publication No. 3-60042
Patent Document 6: Japanese Laid-Open Patent Publication No. 8-242004
Patent Document 7: Japanese Laid-Open Patent Publication No. 2001-188252
Patent Document 8: Japanese Laid-Open Patent Publication No. 2002-343811
Patent Document 9: Japanese Laid-Open Patent Publication No. 2001-83523
Patent Document 10: Japanese Laid-Open Patent Publication No. 2001-21894
Patent Document 11: Japanese Laid-Open Patent Publication No. 2001-109009